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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA CMOS SSI Quad Exclusive "OR" and "NOR" Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. * Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range * Double Diode Protection on All Inputs * MC14070B -- Replacement for CD4030B and CD4070B Types * MC14077B -- Replacement for CD4077B Type MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value MC14070B MC14077B L SUFFIX CERAMIC CASE 632 P SUFFIX PLASTIC CASE 646 IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII Unit V V - 0.5 to + 18.0 Vin, Vout Iin, Iout PD Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg TL - 65 to + 150 260 D SUFFIX SOIC CASE 751A ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = - 55 to 125C for all packages. _C _C Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C 20 ns VDD IDD Vin * CL * Inverted output on MC14077B only. Vin 90% 50% 10% 1/f 50% DUTY CYCLE 20 ns VDD VSS MC14070B QUAD Exclusive OR Gate 1 3 2 5 4 6 8 10 9 12 11 13 MC14077B QUAD Exclusive NOR Gate 1 3 2 5 4 6 8 10 9 12 11 13 VDD = PIN 14 VSS = PIN 7 (BOTH DEVICES) 20 ns Figure 1. Power Dissipation Test Circuit and Waveform VDD PULSE GENERATOR * # VSS CL 20 ns INPUT tPHL OUTPUT 90% 50% 10% 90% 50% 10% tPLH PIN ASSIGNMENT VDD VSS VOH IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C tTHL * Inverted output on MC14077B only. #Connect unused input to VDD for MC14070B, to VSS for MC14077B. VOL tTLH Figure 2. Switching Time Test Circuit and Waveforms REV 3 1/94 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14070B MC14077B 1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I I I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III I I I I I I I I I I III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III III IIII I III IIIIIIIIIIIIIIIIII II II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III IIIII IIIIII III I I I II II III III I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ** The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in H (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Propagation Delay Times** (CL = 50 pF) tPLH, tPHL = (0.90 ns/pF) CL + 130 ns tPLH, tPHL = (0.36 ns/pF) CL + 57 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns Output Rise and Fall Times** (CL = 50 pF) tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.60 ns/pF) CL + 20 ns tTLH, tTHL = (0.40 ns/pF) CL + 20 ns Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 MC14070B MC14077B 2 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Characteristic "1" Level "0" Level "1" Level "0" Level Source Sink Symbol tPLH, tPHL tTLH, tTHL VOH VOL IOH IDD VIH IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 Typ # 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 175 75 55 100 50 40 5.0 5.0 10 15 0 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. IT = (0.3 A/kHz) f + IDD IT = (0.6 A/kHz) f + IDD IT = (0.9 A/kHz) f + IDD 0.00001 MOTOROLA CMOS LOGIC DATA 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 350 150 110 200 100 80 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF ns ns OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01 -A- 14 9 -B- 1 7 C L -T- SEATING PLANE K F D 14 PL G 0.25 (0.010) M N J TA S 14 PL M 0.25 (0.010) M TB S DIM A B C D F G J K L M N P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 8 B 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 A F C N H G D SEATING PLANE L J K M MOTOROLA CMOS LOGIC DATA MC14070B MC14077B 3 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 -B- 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14070B MC14077B 4 *MC14070B/D* MOTOROLA CMOS LOGIC DATA MC14070B/D |
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